Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to Fin-type decoupling capacitors.
In recent years, the need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
In the semiconductor industry, large, planar capacitors formed by two plates separated by a dielectric have been used in many semiconductor designs for the purpose of decoupling noise from power lines. In earlier integrated circuits, much of the decoupling capacitance could be placed off-chip due to the relatively slow cycle times at which such circuits operated. As semiconductor fabrication technologies advance, however, ever increasing device densities have resulted in a need to provide dense capacitors with high capacitance, for various purposes. For example, there are requirements for capacitors for certain analog circuits and functions. Another purpose may be for noise decoupling of power supply nodes. Additionally, the high switching rates used in a modern integrated circuit may cause the power supply voltage to degrade at certain points in the circuit and may cause circuit failures. Decoupling capacitors may be used to reduce supply voltage variations arising from high switching rates in the supplied circuits. These decoupling capacitors are connected between the supply voltage (Vdd) and ground (Vss) in parallel with the supplied circuit. This parallel capacitance tends to decouple the voltage supply from disturbances induced by activity in the supplied circuit and allow the voltage supply to remain at the intended level.
The slow frequency response of off-chip capacitance makes off-chip capacitor arrangements unsuitable for providing the decoupling capacitance necessary to prevent circuit failures in high speed integrated circuit devices.
Accordingly, in order to provide sufficient decoupling capacitance for high frequency circuits, the capacitance must be moved closer to the switching circuitry, onto the integrated circuit chip itself. However, there are various areas of concern in on-chip decoupling capacitor design.
First, the on-chip capacitance should be provided in an area-efficient manner so as not to take up excessive space on the respective chip. Furthermore, on-chip capacitors should be easy to fabricate along with the active and passive circuit elements which make up the desired integrated circuit (i.e., through the same integration). Moreover, different types of decoupling capacitors should be available on the same chip. For example, in certain applications it is desirable to have a thick oxide capacitor. A thick oxide capacitor has lower leakage and higher reliability, however it supplies less capacitance per unit area. Thus, tradeoffs must be made among leakage, reliability, and density. If leakage is less of a concern and the reliability tradeoffs are not big, then a thin oxide capacitor tends to be a better choice.
Using a Fin field effect transistor (FinFET) based technology provides advantages toward high speed CMOS. FETs are the basic electrical devices of today's integrated circuits and are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). A FinFET is one type of FET that has been proposed to facilitate increased device performance. In a FinFET, a vertical “fin” shaped structure is defined to form the body of the transistor. Gates are then formed on one or both sides of the Fin. When gates are formed on both sides of the Fin, the transistor is generally referred to as a double gate FinFET. In particular, the use of the double gate suppresses Short Channel Effects (SCE), provides for lower leakage, and provides for more ideal switching behavior. In addition, the use of the double gate increases gate area, which allows the FinFET to have better current control, without increasing the gate length (also called “gate thickness”) of the device. As such, the FinFET is able to have the current control of a larger transistor without requiring the device space of the larger transistor.
However, using a FinFET based technology to solve the foregoing problems requires a redesign of capacitors. Thus, there is a need for improved and redesigned capacitor structures that incorporate capacitors commonly used in planar CMOS technology into a FinFET based technology.